In a system, data transmission among a plurality of devices is achieved through data buses. It is important to provide adequate data setup time and hold time margins for sampling data when transferring data at high speeds.
Japanese Laid-Open Patent Publication No. Hei 11-85667 discloses a high speed bus system designed to provide adequate data setup and hold times while allowing data to be transmitted at a high speed. Such a high speed bus system will now be described with reference to FIGS. 1 and 2.
Referring now to FIG. 1, a conventional high speed bus system is set forth in a block schematic diagram. The conventional high speed bus system includes a master device 501-1 and a slave device 501-2. Master device 501-1 and slave device 501-2 are connected to clock buses (521 and 522) and data bus 523. Resistors (524 and 525) are respectively connected to an end of clock lines (521 and 522). A reference voltage 527 is connected to an end of data bus 523 through resistor 526. Clock signal tclkM is provided on clock bus 521 from master device 501-1 to slave device 501-2. Clock signal tclkS is provided on clock bus 522 from slave device 501-2 to master device 501-1. Data Data is provided on data bus 523 between master device 501-1 and slave device 501-2.
Referring now to FIG. 2, slave device 501-2 is set forth in a block schematic diagram. Slave device 501-2 includes a reception edge generator 502, data sampler 503, a transmission clock generator circuit 504, and a data output circuit 505. Reception edge generator circuit 502 converts a clock signal tclkM received on clock bus 521 to an internal clock signal RclkB. Internal clock signal RclkB is provided to data sampler 503. Data sampler 503 samples data Data in the same cycle as clock signal tclkM and in synchronism with a clock edge of internal clock signal RclkB.
The conventional high speed bus system provides data transmission between master device 501-1 ad slave device 501-2 as described below.
When data Data is transmitted from master device 501-1 to slave device 501-2, slave device 501-2 outputs clock signal tclkS to master device 501-1 through clock line 522. Slave device 501-2 outputs data Data to data line 522 in synchronism with clock signal tclkS. Master device 501-1 samples data Data based on clock signal tclkS.
In the conventional high speed bus system operating as described above, the device (master device 501-1 or slave device 501-2) providing the data transmission also provides a clock signal (tclkM or tclkS). The provided clock signal (tclkM or tclkS) is used by the device (slave device 501-2 or master device 501-2) that is receiving the transmitted data Data. In this way, an adequate data setup time and hold time is provided and data may be transferred at a high speed.
However, in a conventional high speed bus system having a plurality of slave devices 501-2, slave devices 501-2 may have varying characteristics which can lead to a reduced data setup time and/or hold time. For example, in a conventional high speed bus system having a plurality of slave devices 501-2 and data Data is transferred from master device 501-1 to slave device 501-2, reception edge generator circuit 502 within slave device 501-2 converts clock signal tclkM to internal clock signal RclkB. Internal clock signal RclkB is then used by data sampler 503 to sample data Data. However, in the plurality of slave devices 501-2, characteristics of reception edge generator circuit 502 may vary. Thus, the timing of sampling data Data among the plurality of slave devices 501-2 may also vary. Depending on the amount of variations, an adequate data setup time and/or hold time may only be provided in some of the plurality of slave devices 501-2 and data may not be transferred high speeds.
Also, in the conventional high speed bus system, characteristics of master device 501-1 and slave device 501-2 may vary due to changes in operating conditions, such as operating temperature and power supply voltage. Reduced margins of data setup time and/or hold time may result from such variations in characteristics. For example, when data Data is transferred from master device 501-2 to slave device 501-2 and the characteristics of reception edge generator circuit 502 are varied due to a change in the operating conditions, a rise time and/or a fall time of internal clock signal RclkB generated by reception edge generator circuit 502 may also vary. Reduced margins of data setup time and/or hold time during sampling of data Data may result from such variations in a rise time and/or a fall time of internal clock signal RclkB.
In light of the above discussion, it would be desirable to provide a data transmission system in which margins of a data setup time and/or hold time may be adequate when data is transferred between a master device and slave device. It would also be desirable to provide a data transmission system for transferring data between a master device and a slave device in which margins of a data setup time and/or hold time may not be reduced due to variations of characteristics of the slave device. It would also be desirable to provide a data transmission system for transferring data between a master device and slave device where margins of a data setup time and/or a data hold time may not be reduced due to a change in operating conditions.